Table of Contents
The file name can be one of
Makefile is mostly recommended.
- Include other makefiles
Static file names, wildcards, variables are all supported:
include foo *.mk $(bar)
- Expanded during when
Makefileis parsed, included, etc.
- Expanded during when other expanding rule requires it or actual invoking(target-update)
You can take advantage of
.SECONDEXPANSION special rule and
$$ to defer expanding some prerequisites:
- Wildcard expansions within the definitions of targets and prerequisites are done by
- For recipes, it is done by the
- Variables don't just expand wildcards, they expand only when they are used in targets or prerequisites
- To explicitly expand the wildcard in a variable, Use
-j 3:: run 3 recipes in parallel
-l 2.5:: limit parallelism by load average of
.NOTPARALLEL:: inhibit parallelism
To force some targets to run parallel:
--output-syncoption is not supported the default macOS
make(GNU Make 3.81)
Recursive Use of make
$(MAKE)is the path of
makeexecutable that is invoked
- Some flags for
makeis passed automatically through
- The options
-Ware not put into
usually the name of a file, can also be the name of an action (Phony Targets)
- Phony Targets
- Not refer a file but just the name of an action. They are not prerequisites of something, or does not require some other prerequisites
the names of files that the target depends on
must be indented with
\t, or set
.RECIPEPREFIXto your taste
- Line break : Like many other languages, place
\at the end of the line. Backslash/newlines are converted into a single space character. Once that is done, all whitespace around the backslash/newline is condensed into a single space
When execute the command
- Reads the
Makefilein the currenty directory
<target>'s rule or the first rule if
- Process the rule recursively:
- Process the rule's prerequisites
- Run its own recipe if some of its prerequisites are newer than its own target.
Multiple Rules for One Target
- All the prerequisites mentioned in all the rules are merged into one list
- There can only be one recipe to be executed for a file.
- When there are serverl recipes for a file,
makeuses the last one given and prints an error message.
Static Pattern Rules
- Each pattern normally contains the character
$<is the automatic variable that hold the name matched by
$@is the automatic variable that hold the name of the target
- Each implicit rule has a target pattern and prerequisite patterns
- There are built-in rules for common languages
when x.c, y.c and z.c all exist will execute:
- A pattern rule contains the character
%(exactly one of them) in the target
Double Colon Rules
- Normally, one file can be the target of several rules, and in this case, the prerequisites of the rules are merged.
- When rules are specified with
::, the rules and their prerequisites are treated separatedly.
- There are special built-in target names to adjust
- Prevent the name collision between files and actions
- Prevent rules from not being treated as a implicit rule.
- Just a usual thing
- Placed after
|, just specify the dependency, but not triggers the target even if it's newer.
$ make a touch c touch b touch a $ make x touch z touch y touch x $ make a make: `a' is up to date. $ make x make: `x' is up to date. $ touch c $ make a touch b touch a $ touch z $ make x make: `x' is up to date. $ rm c $ make a touch c touch b touch a $ rm z $ make x touch z
- Recipe lines are echoed by default
- When a line starts with
@, the echoing of that line is suppressed.
@is discarded before the line is passed to the shell.
Shell for Recipe
SHELL = <path-to-shell>
.SHELLFLAGS = <flags>
.ONESHELL:to do all invokations in a shell
- Unlike most variables, the variable
SHELLis never set from the environment.
Errors in Recipes
- To ignore errors in a recipe line, write a
-at the beginning of the line’s text
When the same sequence of commands is useful in making various targets:
- Variable names like
.UPPERCASEmay be given special meaning in future versions of make.
- Variable names are case-sensitive
- It is traditional to use upper case letters in variable names
- It is recommended to use lower case letters for variable names that serve internal purposes in the makefile
- Every environment variable that
makesees when it starts up is transformed into a
makevariable with the same name and value.
- Explicit assignments will override the variables from environment.
makeruns a recipe, variables defined in the
Makefileare placed into the environment of each shell.
- $(origin variable)
- tell the source of the variable, like
Define custom functions
- There is no explicit function definition, but it can be mimicked using define directive along with $(call variable,param,param,…)
Every Makefile should contain this line:
SHELL = /bin/sh